Cache/Memory Coordinated Fair Scheduling for Hybrid Memory Systems
Di Chen, Haikun Liu, Hai Jin, Xiaofei Liao · 2020
Hybrid memory systems comprising DRAM and Non-Volatile Memory (NVM) have gained ever-increasing attention for building large-capacity and energy-efficiency main memory. Nevertheless, there remain challenges to best utilize them because of the asymmetrical access latencies of DRAM and NVM. Traditional memory request scheduling schemes usually lead to notable application performance degradation and unfairness. In this paper, we propose a cache/memory coordinated (CMC) memory request scheduling strategy to address inter-process memory interference and unfairness scheduling problems in hybrid memory systems. Taking the asymmetrical access latencies into account, CMC leverages average access time (AST) to quantify inter-process memory interference in hybrid memory systems. CMC preferentially schedules applications with a small number of memory requests, while schedules memory-intensive applications according to their AST. CMC further filters some memory blocks with poor locality to improve the efficiency of last level cache (LLC). Experimental results show that CMC improves system performance and fairness by up to 16% and 9% than traditional first-ready-first-come-first-service (FRFCFS) memory scheduling policies, respectively.