First Time Miss : Low Overhead Mitigation for Shared Memory Cache Side Channels
Kartik Ramkrishnan, Stephen McCamant, Pen-Chung Yew, Antonia Zhai · 2020
Cache hit or miss is an important source of information leakage in cache side channel attacks. An attacker observes a much faster cache access time if the cache line has previously been filled in by the victim, and a much slower memory access time if the victim has not accessed this cache line, thus revealing to the attacker whether the victim has accessed the cache line or not.