Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processors
Abhijit Das, Kumar Abhishek, John Jose, Maurizio Palesi · 2020
To meet the worst-case performance requirements, on-chip routers in Tiled Chip Multi-Processors (TCMPs) are provisioned with input port buffers. However, in real applications, the average buffer utilisation in routers is significantly low except during peak network congestion. In this work, we exploit the idle buffers in Network-on-Chip (NoC) routers to store dirty cache blocks evicted from the L1 cache. Future requests for such recently evicted cache blocks are serviced from the router buffer, thereby significantly reducing the cache miss latency. We propose two variations on how long we can store these evicted cache blocks on NoC router buffers; one up to a time threshold and another up to the arrival of a demand from an L2 cache bank. We make architectural modifications on the buffer management circuitry of NoC routers to make sure that the evicted, dirty cache blocks are stored in the local routers for the longest duration possible to facilitate local reply. Experimental results show that our proposed modifications achieve a maximum system speedup of up to 15% and an average system speedup of 12%.