Area-Efficient Pipelined VLSI Architecture for Polar Decoder
Weihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao · 2020
Polar codes have attracted increasing attention recently due to its low encoding and decoding complexity. Hardware optimization can further improve their implementations to enable real-time applications on resource-constrained devices. This paper presents an area-efficient architecture for Successive Cancellation (SC) polar decoder. Our proposed architecture adapts the optimization techniques from Fast Fourier Transform (FFT), and applies high-level transformation methods including folding, pipelining, and retiming, to reduce the number of Processing Elements (PEs) to only log_2N for an N-bit code. Additionally, the pre-computation technique is utilized in the PE design to allow decoding 2 bits in parallel. We also propose a customized loop-based shifting register to further reduce the consumption of delay elements. Our experimental results demonstrate that our architecture reduces 98.86% and 77.71% on average in area consumption and area-time product, respectively, when N = 1024, compared to the prior works.