A New Register Transfer Level Synthesis Method for ASIC Design
Chi-Ho Lin · Journal of IKEEE · 1999
This paper presents a new register transfer level synthesis method to overcome the disadvantages of the previous register transfer level synthesis systems. The previous register transfer level synthesis systems first translate from a hardware description language to sequential circuits inadequately. Secondly, the systems separate registers and combinational circuits and then optimize only combinational circuits. This paper describes their disadvantages and then proposes a new method to overcome their shortcomings. This paper also shows the effectiveness of the proposed method by using the proposed method at designing the controller of a surveillance system and the 8-bit signed multiplier.