McCMOS Based Low Power and High Speed 32 x 32 Bit Nikhilum Multiplier
Sarita Chauhan · CyberLeninK (CyberLeninka) · 2020
Leakage power is the significant component of total power dissipation in nano-scale devices. Leakage power is inversely proportional of channel length. So as the device dimensions are reduced, to incorporate more no of devices, for more function to be performed, subthreshold leakage current & hence leakage power will increases. To reduce the leakage power, channel length has to be increased. So we use non-minimum length transistors to reduce the leakage current thus power. This technique is called Multiple Channel CMOS (McCMOS). Vedic mathematics is the branch of mathematics which depends upon 16 sutra and 13 up-sutra, given between 1911 and 1918 by Sri Bharati Krisna Tirthaji (1884-1960). In this paper we had used McCMOS technique as well as ancient Vedic technique Nikhilum Sutra to reduce the power dissipation and increase the speed of the multiplier. The designed 32 x 32 bit multiplier dissipates a power of 0.556 mW and a propagation delay of 27.82 nsec. 60510 transistors were used in this design. These results are improvements over power dissipations and delays reported in literature for Vedic and Booth Multiplier.