Code with Crosstalk Avoidance and Error Correction for Network on Chip Interconnects
Kandala Anupama Satya Sai Lakshmi, A. M. Keerthi, Kuruganti Madhu Sri, M. Vinodhini · 2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184) · 2020
Efficient design of encoder and decoder for error identification in Network on Chip (NoC), contributes an important factor in reliable data communication. Though NoC has improvised the routing process, it still has few challenges to overcome. The key challenge for NoC is error identification during transfer of large data bits between routers and to depreciate the noise between data bits. This paper gives a description of the technique that has been developed for the design of encoder and decoder for error identification and correction using the parity sharing techniques for data communication between routers. The developed encoder uses crosstalk reduction technique in order to diminish the crosstalk between the data bits. In this paper, 32 bit data transfer has been considered between routers of NoC and 20 parity bits are calculated using parity sharing technique. Since crosstalk is observed between the data bits, two-folded the data bits are two-folded at the encoder to depreciate the noise. Also, an algorithm has been designed to distinguish and rectify the corrupted bits at the decoder. The proposed method ensures more reliability, less power consumption, time delay and area compared to other state of art techniques.