RIDE: Energy Efficient Data Allocation on Compound Racetrack-SRAM Scratchpad Memory for Real-Time Embedded Systems
Alireza Lotfi Takami, Ali Hoseinghorban, Mostafa Bazzaz, Alireza Ejlali · 2020
Embedded systems have time and energy constraints; so, they use scratchpad memory (SPM) as on-chip memory to replace cache. SRAMs low access latency makes it an excellent choice for on-chip memory, but SRAM has a low density and high static power consumption. Non-volatile memories (NVMs) spend high energy and time regarding the write operation while they have the benefits of high density and low static power. Therefore, a compound on-chip memory, which exploits the advantages of SRAM and NVM, could elevate the energy and time efficiency. In this research, we suggested RIDE a compound SPM and data allocation strategy consisting of SRAM and racetrack memory (RTM) to improve both energy usage and performance. RIDE dedicates a large area of on-chip memory to RTM to minimize energy consumption. Considering that RTM needs shift operation to access memory, and it has high write access overhead, RIDE used a small SRAM alongside the RTM to reduce the number of shifts, energy, and latency of RTM. Furthermore, we introduced a novel data allocation for RIDE, which helps to determine the best memory for each data in an application to improve energy and performance, while it considers the worst-case execution time (WCET) of the system. Experiments demonstrate that RIDE alleviates the power usage and execution time of the memory subsystem up to 63% compared with the other novel on-chip memory designs. RIDE increase WCET of applications by less than 1% on average, compared to pure SRAM architecture.