Design of Compact Modified Radix-4 8-Bit Booth Multiplier
Trio Adiono, Hans Herdian, Suksmandhira Harimurti, Tengku Ahmad Madya Putra · International Journal on Electrical Engineering and Informatics · 2020
The conventional serial booth multiplier generates full partial product (2n+1) and it require a 2n bit adder to perform the operation.Because of that the area of the circuit will be inefficient.Modified booth algorithm is used to reduce the number of partial product calculation to only half of the serial-parallel multiplier implementation, while keeping the area is still in acceptable level.In order to optimize the area, we propose a design by modifying the architecture of radix-4 modified booth multiplier.Here, we customize the architecture by sharing the registers and minimizing the bit size of adder.For the adder block, we further optimize the design by combining the ripple carry and carry look-ahead adder in order to eliminate the need to create separate circuit for receiving many signal inputs.The carry look-ahead segment is implemented using static Manchester Carry Chain because of its high speed, small size, and consistent performance.The design is implemented using 0.13µm CMOS technology.From the implementation and post-layout simulation result, the total number of transistor that is used is 1132 and the total combination delay is 340 ns.