High-speed AWG exploiting parallel time interleaved DAC cores
Mauro D’Arco, Leopoldo Angrisani, Pietro Monsurrò, Alessandro Trifiletti · 2020
An arbitrary waveform generator architecture that exploits multiple DAC cores to increase the sample rate with respect to AWG architectures based on an individual DAC is proposed. The processing operations necessary to distribute the waveform samples between the DAC cores are illustrated. The preliminary results highlighting the performance expected from the proposed architecture are shown.