Design of Single-Bit Fault-Tolerant Reversible Circuits
Hari Mohan Gaur, Ashutosh Kumar Singh, Anand Mohan, Masahiro Fujita, Dhiraj K. Pradhan · IEEE Design and Test · 2020
This article introduces redundant design approaches for reversible circuits that have the ability to detect and tolerate single-bit fault without the need of conventional voting scheme. Experiments preformed show that the proposed scheme reduces the gate cost on average with up to 28% as compared with tri-modular redundant circuits.