Hardware implementation of a multi-mode hash architecture for MD5, SHA-1 and SHA-2
Sylvain Ducloyer, Romain Vaslin, Guy Gogniat, Eduardo Wanderley · 2007
Abstract — In this paper, we propose a unified architecture adapted to the field of embedded systems which combines com-monly used hash algorithms in a single design in order to reduce area requirements and optimize the maximum frequency. We present an implementation of three hash functions: MD5 [8], SHA-1 [9] and SHA-2 [10]. Many similarities exist between these algorithms which help us to move towards a unique architecture. The design was implemented on an Altera Stratix II device. It only requires 3311 ALUTs and operates at a frequency of 93 MHz which provides a throughput of 567 Mbps for MD5/SHA-2 and a