The Minimizating of Hardware for Implementation of Pseudo LRU Algorithm for Cache Memory
Вадим Олексійович Пуйденко, Vyacheslav Serhiiovych Kharchenko · 2020
the synthesis of the synchronous digital automaton with the logic of the pseudo LRU algorithm is carried out taking into the account events of hits or misses inside the associative cache memory. The synchronous digital automaton's model with the controlling logic for management substitution of data elements at the full reliability of the selected data's multitude is described. The minimizating for the switching functions that are simple completely defined and composite not completely defined are carried out. They are switched as: L = λ(B) by selecting multiple among reliable values and B+= f(B, λ(B)) forming the values of bits for unit LRU considering the previous state. As a result the minimum discrete realization has been obtained by suggested hardware solutions substitution policy for the algorithm of pseudo LRU of internal associative cache memory.