Novel High-Speed Low Power Hybrid Full Adder: Design and Analysis
Venkat Subba Rao. Manchala, Damale Prasad Rajendra · Journal of Critical Reviews · 2020
This paper explores a novel design of a hybrid 1- bit full adder (FA)[1].This design can be low power conditions[2]. This novel Hybrid Full Adder (FA) design was formed based on the two logics that are Transmission gate (TG) and swing restorer logic[2][3]. By using swing restorer logic and Transmission gate(TG) at output terminals of adder circuit (sum, carry) produces the full swing, less short circuit power compared to pass transistor logic[4][7]. This proposed hybrid full Adder (FA) design doesnt have a cross-coupled and positive feedback connection at the output side of the critical path to avoid the short circuit power loss and internal capacitance in the circuit[1][8]. So, the proposed design has less delay and high speed compared to existing Pass transistor logic (PTL)[4][2]. Simulation results in Cadence Virtuous Tools of 90nm 180 nm technology nodes[13][17]. The investigation has been carried out and reveals that the total numbers of the transistor are reduced from 18T to 14T in the proposed design[3][10]. The proposed design has an average Power Consumption is 1.337 µW Supply Voltage of 0.9V in 90nm and 101.0 µW at1.8V supply voltage in 180nm technology. The amount of propagation delay calculated as 0.139ns and 4.775ns for both 90 nm and 180 nm technologies respectively. Thus, the novel hybrid Full Adder design has superior performance parameters compared to existed design. Thus, hybrid one bit Full Adder design was well suited for Low Power High Speed operation Applications.