A Quasi-Static Storage and Decision Block for Performance-Efficient Content Addressable Memory
Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat · 2019 IEEE 6th International Conference on Engineering Technologies and Applied Sciences (ICETAS) · 2019
Content addressable memory (CAM) is used as a hardware in lookup intensive applications. Despite high-speed feature, power consumption is the major limitation in CAM design. In this work, a compact CAM cell employing a high-speed comparison and evaluation is presented for a segmented NOR match-line (ML) with reduced ML capacitance. The non-pipeline CAM architecture minimizes switching activity of precharge and search at the cost of negligible overhead of a ML precharge and decision block. A 64×32-bit proposed macro is realized using 45-nm CMOS technology. Post-layout simulations at 1.1 V shows that proposed architecture achieves 203.60 ps search time while dissipating only 1.07 fJ/bit/search. Consequently, it leads to 71.24% and 84.85% energy-delay-product reductions over a conventional CAM and local-NOR global-NAND CAM, respectively. The proposed CAM based on two-segment configuration delivers ML power reductions of 12.26%-62.27% over the two CAMs. The proposed design is capable of operating efficiently at relatively low supply voltage and worst process corner.