Implementation of Viola-Jones Algorithm for Object Detection Using FPGA
Felix Noel Sitorus, Yustina Manihuruk, Good Fried Panggabean · 2019
This research presents the design and implementation of hardware for face detection based on the system of the Viola-Jones Algorithm in the Field Programmable Gate Array (FPGA) using VHSIC Hardware Description Language (VHDL); VHSIC (Very High Speed Integrated Circuit). The data used in this study is based on real conditions and uses sample images where in this research we use the images sample with dimensions 450×375 pixels which is like the resolution of webcam that using for the Xilinx Zybo (Zynq Board). In this research, the proposed architecture is using VHDL and implemented in Xilinx Zybo Zynq-7000 ARM/FPGA SoC Trainer Board. To measure the performance of the FPGA-based face detection system from the Viola-Jones Algorithm, the number of frames processed per second (FPS) must be measured, where the processes must be designed which are divided into two types of partitioning, there are software and hardware designs. This is accomplished by measuring the time elapsed from capturing an image to displaying the detection results. More specifically this is the time elapsed from the start of a frame capture to the end of drawing face bounding boxes on to the captured image. An experiment was conducted to gather the minimum, maximum and average FPS of FPGA face detection system of the Viola-Jones Algorithm. From the process of this research we've been got hardware latency just for the 3rdmodules implemented is 125,207 millisecond, whereas software implemented (run on ARM Cortex 9 / Hardcore Zybo Processor) is 3642,993 millisecond, so speedup by implementing these 3 modules as a hardware accelerator is 29,095 rounds.