Low power high performance priority encoder using 2D-array to 3D-array conversion
Kailash Chandra, N. S. Murty · Procedia Computer Science · 2020
This paper discusses priority encoder and its designing complexity for higher number of input bits, i.e., 64, 128, 256, and so on. In order to reduce the complexity and power consumption of the circuit, a new circuit with three-directional (3D) array priority encoder is introduced. This 3D-array priority encoder circuit reduces the power consumption by 23.908 % and the transistors count by 19.572 % using 180nm technology, by using 45nm technology power consumption is reduced by 23.588% and transistors count remains same when compared to the existing two-directional (2D) array priority encoder. In this paper 64-bit input priority encoder is implemented using Cadence Virtuoso GPDK-180 nm and 45nm technology.