RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation
Irith Pomeranz · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020
Reverse order fault simulation and its variations provide a test compaction option with a low computational effort that is applicable even when test constraints or complex fault models preclude the application of other conventional test compaction procedures. This is the scenario considered in this brief. Reverse order fault simulation procedures remove unnecessary tests from a test set without otherwise modifying it. Reverse order fault simulation is typically applied once after the complete test set has been generated. This brief observes that when other test compaction procedures are not applied, forward-looking reverse order fault simulation sometimes yields a smaller test set if it is applied more often during the test generation process. However, applying it more often also increases the computational effort. This brief explains this phenomenon and describes a procedure that uses the new insights to improve the ability of forward-looking reverse order fault simulation to achieve test compaction at a reduced computational effort. The experimental results for benchmark circuits are presented to support the discussion.