Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling
Ashutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, Deming Chen · 2020
FPGA-based computation has shown better latency and energy efficiency compared to CPU or GPU-based solutions. However, as the complexity of emerging applications has significantly grown, it is difficult to efficiently utilize the FPGA. Thus, there is a renewed interest to deploy dynamic partial reconfiguration for FPGA-based hardware from both the industry and the academic community. In this work we demonstrate a methodology for scheduling heterogenous tasks across given FPGA resources in a resource efficient manner while effectively hiding latency of dynamic partial reconfiguration. With the help of an ILP based scheduler, we demonstrate the mapping of diverse computational workloads in both cloud and edge-like scenarios. Our novel contribution includes enabling pipelining and parallelization of batches in our scheduler. Our scheduler is capable of masking reconfiguration overheads, and its ability to pipeline across batches demonstrated up to 3.9X improvements. Finally, our scalable scheduler is capable of simultaneously mapping 11 applications to a single cloud-scale, as well as edge-scale, FPGA.