Thyristor Operation for High Speed Read / Program Performance in 3D Flash Memory with Highly Stacked WL-Layers
Hideto Horii, Takashi Maeda, Tomoya Sanuki · 2020
We have demonstrated the thyristor operation that achieved high speed read / program performance in 3D flash memory with highly stacked WL-layers. To our best knowledge, this is the first time to successfully overcome smaller read current and strong cell-to-cell interference problem in the thyristor operation by setting relevant BL and WL bias condition and optimizing device structure of 3D string. The thyristor operation can provide over 3 times larger read current than the conventional MOS operation even in more than 100 stacked layers. In addition, our novel WL bias scheme could successfully suppress cell-to-cell interference and enables multi-level cell operations. The overall system performance is improved for both read / program latency by 15 % / 10 % in SLC mode and 20 % / 15 % in QLC mode, respectively. Even with large read current, the energy consumption of the thyristor operation is equivalent to that of the conventional MOS operation owning to its high speed performance.