Optimal Realization of Full Adder in QCA using 5-input majority gate
Trailokya Nath Sasamal, Anand Mohan, Ashutosh Kumar Singh · 2020
This work showcases an optimal layout for 5input majority gate, that occupy less QCA area when compare to existing gates. A new QCA layout of Full adder has demonstrated to showcase the applicability. To consider realistic clock distribution, we have utilized USE (Universal, Scalar and Efficient) clocking technique for implementing the Full adder. QCAdesigner based results confirmed that the presented structure has outperformed existing designs taking QCA cells, area occupied and clock delay as design metrics. Proposed design shows 45% drop in cell numbers and requires 78% reduction in area when compare to previous superior design implemented on existing clocking techniques.