Minimising Impact of Local Congestion in Networks-on-Chip Performance by Predicting Buffer Utilisation
Aqib Javed, Jim Harkin, Liam McDaid, Junxiu Liu · 2020
Networks-on-Chip (NoC) were designed to enhance the communication performance of Multi-processor Systems-on-Chip (MPSoC). NoCs are equipped with buffered input channels which queue incoming data and minimise routing stress especially under uneven traffic distributions. Buffer utilization of a router node provides an early indication to potential local congestion. In this work we propose a novel Spiking Neural Network (SNN) based congestion prediction model to predict input buffer utilization as a congestion parameter to minimize impact of potential local congestion. Router-level and Network-level models are proposed in predicting congestion at each NoC router node. Results show that the router and network models can predict buffer utilization patterns with an average accuracy of 91.89% and 93.76%, respectively.