Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC
Pedro Lima, Caio Vieira, Jorge Reis, Alexandre Almeida, Jarbas Silveira, Roger C. Goerl, Cesar Augusto Missio Marcon · 2020
Increased device integration has enabled the construction of complex System-on-Chip (SoC) architectures, enabling it to meet the increasing demand for functionality required by emerging embedded applications. Among these architectures is MultiProcessor SoC (MPSoC), which is made up of a processor set containing an Instruction Set Architecture (ISA) with sometimes underused and high-cost implementation instructions, increasing power dissipation and area consumption and losing performance due to the increased critical path. This work proposes an MPSoC that extends the standard ISA of the RISC-V architecture through shared resources among processors. The strategy proposed is to execute instructions in specialized modules distributed in the system when the processor's datapath do not support them. To evaluate the proposed methodology, we implemented a set of scenarios that were evaluated for area consumption, power dissipation, energy consumption, maximum operating frequency, and the number of cycles for the application execution. The experimental results show that, with a low hardware cost, the proposed resource sharing technique reduces several metrics with a low penalty in the execution time of the analyzed applications.