Bit-line Keeper based Computational Memory Architecture: varieties and comparisons
Driss Azougagh, Ahmed Rebbani, Omar Bouattane · 2020 1st International Conference on Innovative Research in Applied Science, Engineering and Technology (IRASET) · 2020
The Computational Memory Architecture (CMA) is composed of interconnected and controlled compute-lines (CL). CL supports in bit-line processing that brings parallel computation as close as possible to the location of the stored data. CL supports in memory computing without requiring dedicated computational, pre-charging and/or sensing (logic) circuits. Instead, it uses a bit-line keeper (KEEPER) to keep both bit-lines stable and superposed to each other when requested by the controller. It first selects and sets up an operation, reads bit information from participating inputs (local memory cells) in parallel and simultaneously, stabilizes the bit-lines throughout the controlled KEEPER, and finally writes the data to the target outputs (local memory cells) in one compute cycle. CMA introduces promising potentials to cope with the growth of Big Data, memory wall and power wall. It can support many dedicated network topologies by interconnecting inputs and outputs of its CLs. Using dedicated topologies, CMA may significantly benefit many existing research areas such as applications in neural network and/or deep learning. In this work, we introduce a comparison study and analysis of four different bit-line keepers; Minimal, Enhanced, Power-saving, and Unpowered KEEPERs (M/E/P/U-KEEPERs). E-KEEPER, P-KEEPER and U-KEEPER omits any dedicated commands from the compute-line controller and reduces power consumption in comparison to M-KEEPER by factors of 1.93, 3.63 and 3.68, respectively.