256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers
Dongku Kang, Woopyo Jeong, Chulbum Kim, Doo-Hyun Kim, Yong Sung Cho, Kyung‐Tae Kang, Jinho Ryu, Kyung-Min Kang, SungYeon Lee, Wandong Kim, Hanjun Lee, Jaedoeg Yu, Na-Young Choi, Dong-Su Jang, Cheon An Lee, Young-Sun Min, Moo‐Sung Kim, An-Soo Park, Jae-Ick Son, In-Mo Kim · IEEE Journal of Solid-State Circuits · 2016
A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively. Also, to maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique with temperature compensation is introduced. The chip, fabricated in a third generation of V-NAND technology, achieved a density of 2.6 Gb/mm2with 53.2 MB/s of program throughput.