A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design Verification
Shumaila Qamar, Wasi Haider Butt, Muhammad Waseem Anwar, Farooque Azam, Muhammad Qasim Khan · 2020
Universal Verification Methodology (UVM) is getting attention of researchers and functional verification community due to its advance flexibility, reusability and reliability features for design verification of multifaceted embedded systems. This is the reason that different tool vendors like Mentor Graphics support UVM-based simulation for design verification. Similarly, researchers frequently explore / utilize UVM to enhance the verification capabilities for embedded systems. In this context, there is a strong need to summarize the latest advancements, tools and techniques for UVM standard. Therefore, this article performs a Systematic Literature Review (SLR) to identify 27 studies (i.e. 2017-2019) pertaining to UVM standard. Subsequently, 21 UVM-based frameworks and 9 tools are identified. Moreover, key benefits of UVM standard are investigated. Finally, a comparative analysis of UVM with OVM (Open Verification Methodology) is performed. It is concluded that UVM provides advanced phasing mechanism, reporting, callbacks, objections, sequence libraries and control over simulation as compared to OVM. Researchers and practitioners of domain can highly benefit from findings of this article.