Research of the Efficiency of High-level Synthesis Tool for FPGA Based Hardware Implementation of Some Basic Algorithms for the Big Data Analysis and Management Tasks
Alexander Antonov, Denis Besedin, Alexey S. Filippov · 2020
The article is devoted to a research of an efficiency of high-level synthesis approach, based on Xilinx's high-level synthesis tool - Vivado, for a hardware implementation of sorting algorithms, which are one of the key algorithms for Big Data analysis, Data Mining, Data and Management. Performance and hardware costs are the measures of the efficiency in the provided research. The research methods are simulation and comparative analysis. Efficiency of software implementation of the selected sorting algorithms, based on a universal processor, is compared with efficiency of hardware implementation of the same sorting algorithms, obtained by high-level synthesis procedure with help of Xilinx's high-level synthesis tool. The article discusses approaches to optimize the description of the sorting algorithms and assignments in boundaries of high-level synthesis procedure to achieve optimal efficiency of the final hardware solutions. The article shows that the main efficiency gain is determinate by the internal features of the sorting algorithm, selected for hardware implementation; the ability to parallelize the processing of the source arrays, which is achieved both by the settings of the Vivado synthesis tool and description style used for source code. Article highlights research results and provide a direction for the future research works.