An Area and Delay Efficient Logarithmic Multiplier
Navteja Alla, Syed Ershad Ahmed · 2020
Multiplication is an ubiquitous operation in growing set of media processing applications (graphics, audio, video, and image). Many of these applications, however, possess an inherent quality of error resilience. Thus the multipliers, that are not very precise but return an approximate value, can be utilized in such applications. Such units, it may be anticipated, may result in area savings while also resulting in reduced power consumption. In recent years, logarithmic number system (LNS) has been increasingly used as an alternative to the binary number system as it converts multiplication to addition resulting in simplified hardware. However, they suffer from inherent error and any efforts in improving their accuracy would help find their increased usage in arithmetic computations with efficient hardware. In this paper, a method that combines Mitchell's approximation with a hardware pruning technique that leads to an area efficient multiplier architecture without compromise on precision. Simulations carried out prove that the proposed multiplier architectures are efficient both in area and delay when compared to existing designs.