Reconfigurable DWT unit based on lifting
Georgi Kuzmanov, Bahman Zafarifar, Prarthana Shrestha, Simon Vassiliadis · 2002
Abstract ⎯ At algorithmic level, the so-called lifting scheme represents the fastest implementation of the Discrete Wavelet Transform (DWT). In this paper, a hardware accelerator for the lifting scheme is described. A liftingbased DWT unit was implemented in reconfigurable hardware, namely the Xilinx VIRTEX II FPGA. The hardware module achieves the acceleration using techniques as pipelining, data re-usability, parallel operating sub-units and some specific features of the Xilinx FPGAs. A VHDL model was developed and synthesized with the implementation tools of the FPGA vendor. Synthesis results prove the feasibility of a 50 MHz FPGA implementation, allowing processing rates between 85 and 1087 pictures per second for a range of standard picture dimensions. To estimate the performance gains from the hardware module, we compare these results against a pure software implementation of the algorithm from the LIFTPACK software package. For picture size of 720 x 560 pixels, assuming clock frequency of 50 MHz for the hardware module, simulation results indicate a speed-up of over 5 times versus a pure software realization on a 1 GHz general purpose MIPS processor. Moreover, the speed-up grows for larger images and filters with higher degrees. The hardware area costs are estimated to be 985 Virtex II CLB slices, 669 Flip-Flops, 22 Block RAM and 8 multiplier blocks for a basis structure. The design is generic and scalable, which allows better performance when more parallel sub-units are implemented.