Performance Improvement for Stacked-Layer Data Bus Reconstruction on Complete Timing Period
Chia‐Chun Tsai · 2019
In this paper, we proposed an algorithm to improve the bus performance by reconstructing a stacked-layer data bus. The algorithm always tries to insert repeaters into the current critical path of a data access for isolating their extra capacitive loadings and sizes their repeaters for minimizing the critical access time on a complete timing period. The above process is repeated until no any improvement in the critical access time. Finally, each access time and the average access time can be dramatically decreased and the bus performance thus be upgraded. Experimental results show that our performance improvement for a stacked-layer data bus on a complete timing period has up to 49.15% in average access time on average and has 17.95% better than other approaches.