Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism
Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2020
The IEEE Std. 1687 facilitates flexible access to on-chip instruments through the JTAG test-access port. This flexibility enables the minimization of the overall access time (OAT), and a number of techniques have been proposed in the literature to achieve this goal. However, the OAT is still high for instruments that require a large amount of test data if this data is shifted through the scan chain serially. In order to further reduce the OAT, we present an efficient test-scheduling method that exploits broadcast and hardware parallelism for instrument access. A broadcast scheduling method is synergistically combined with three parallel IJTAG designs. We show that under different cost criteria, we can select the most efficient parallel IJTAG design such that the equivalent access time (EAT) is minimized. In addition, an interconnect fabric design and an integer-linear-programming method is used to balance the lengths of multiple scan chains. Two industry chip designs and three IJTAG benchmarks are used to evaluate the effectiveness of the proposed method.