Design of Pipelined Parity Preserving Double Precision Reversible Floating Point Multiplier Using 90 nm Technology
F. Mhaboobkhan, K. Kokila, R. Jothikha, K. Lakshmi Preethikha · 2020
In semiconductor industries, speed of operation and the size of the computational devices are playing a major role. Size of a single transistor may limit the scaling of semiconductor devices. In turn, an alternative technology is needed for faster computation and to reduce the size of computational devices. One such technology is Reversible Logic. Parity preserving is a property that is added to reversible gates with the help of which, presence of errors can be detected. In this Paper, Parity Preserving Reversible Floating point multiplier (RFPM) which uses IEEE 754 standard representation is proposed using P2RG and Fredkin Reversible gates. This RFPM uses Carry select adder for Exponent addition and Carry save Multiplier for Mantissa multiplication. The architecture also includes a multiplexer, Bit slicer, rounding and normalization register. This Pipelined RFPM architecture is coded using Verilog and the same has been simulated using Modelsim 10.7c. Parameters such as Area, Power, Cell Utilization and Maximum operating frequency have been analyzed using Cadence Genus Synthesis 14.25. On Comparison of Pipelined RFPM with Non Pipelined RFPM between 180nm and 90nm technology, the results show that Pipelined RFPM using 90nm technology, occupies lesser Area and uses lesser number of cells by 67.17% and 4.42% respectively whereas, the Maximum operating frequency has increased by a factor of 2.73.