Abstract - HOTI 2019: Compute Express Link
S. Van Doren · 2019
Summary form only given. Compute Express Link (CXL) is an open industry standard interconnect offering high-bandwidth, low latency connectivity between host processors and devices such as accelerators, memory buffers, and smart I/O devices. It is designed to address the growing high-performance computational workloads by supporting heterogeneous processing and memory systems by enabling cache coherency and memory semantics. This talk will start with an introduction to CXL, describing its alignment to the PCIe eco-system at the physical layer, the communication paths in the legacy PCIe eco-system that CXL aims to improve, and the basic elements of the CXL protocol that will provide these improvement opportunities. It will also walk through three of what are expected to be the most common usages for CXL. With the basics of CXL introduced, this talk will focus on three of the key elements of CXL: CXL's link layer, CXL asymmetric coherency protocol and CXL's "Coherence Bias" technology. CXL takes an unusual approach in its link layer, but one that aligns well with its target usages. The talk will describe the link layer, the cost of the CXL choice versus other alternatives and the benefits that come with the CXL choice. CXL also takes a unique approach to cache coherency between processors and devices with its asymmetric coherency protocol. The talk will describe this asymmetric approach, contrast it to more standard symmetric cache coherency protocols and walk through some of the trade-offs between symmetric and asymmetric protocols, in particular noting the implications for memory disaggregation usages and device development. Finally, this talk will discuss CXL "Coherence Bias", a technology that is unique to CXL. It is a technology that allows software to modulate hardware performance characteristics in accordance with the operational phases of an application. This technology leverages the fact that the software eco-system for heterogeneous computing provides an opportunity for software to overcome some of the downsides that come with the use of cache coherency in between processors and offload devices.