A 125 mm/sup 2/ 1Gb NAND flash memory with 10 MB/s program throughput
Hiroki Nakamura, K. Imamiya, Toshihiko Himeno, Takuji Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, K. Kawai, R. Shirota, N. Arai, F. Arai, K. Hatakeyama, Hiroaki Hazama, Masato Saito, H. Meguro, K. Conley, Khandker N. Quader, Jian Chen · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003
A 125 mm/sup 2/ 1Gb NAND flash uses 0.13 /spl mu/m CMOS. The cell is 0.077 /spl mu/m/sup 2/. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.