Hardware Trojan detection with node reduction using static timing analysis
R. Keerthykrishna, M. Priyatharishini, M. Nirmala Devi · AIP conference proceedings · 2020
Globalisation of the Integrated Circuit (IC) is making it easy for the adversaries to pirate IC and insert hardware Trojans. Hardware Trojans are detected at an early stage i.e. the RTL design stage by the verification technique by applying all the input patterns exhaustively. But the Trojans are becoming stealthier and they can easily evade the verification technique. In this paper, a transition probability and timing analysis based Trojan detection is proposed. As at each stage the nets are getting filtered out and thus reducing the execution time and complexity of the technique. So the Trojans which evades the design stage detection technique can be easily caught by the proposed technique as it based on the side channel analysis. This method is verified on ISCAS’85 and ISCAS’89 circuits.