Carry Chain Test of Xilinx FPGA
Zong Jie Xiang, Liheng Wang, Lanlai Wang, Xiaohai Hu, Junjun Wan · 2019
This paper proposes a method for the carry chain test of the Xilinx FPGAs. The method is a build-in-self-test one. It needs only a few intentionally designed inputs which is equivalent to all of the possible combinations, and therefore no longer needs a large number of randomly generated inputs to cope with combination explosion. Some series of Xilinx FPGAs have vacant areas where no carry chain exists. The vacancy creates difficulty for testing. We develop a method to solve this problem. The theory of our method and FPGA implementation results demonstrate that our method is elegant in test coverage and efficiency.