Improved Pipeline Inner Product Computation Unit for Binary Numbers
Binta Lamba, Anurag Sharma · 2018
we proposed floating point fused multiply add unit for binary numbers operating at 16 GHz. This is designed using floating point pipelined operation with Booth multiplier. A floating point pipeline is designed to compute the partial products. A floating point fuse multiply adds unit is proposed to be designed using a kogge stone adder. Floating point pipeline multiplier must be operated with 32-bit operands in parallel. In the last step we compute the final product of partial products. The new products of 32*32 bit binary numbers are obtained by every clock cycle. The worst computation time measured amid the floating point pipeline is 0.042 ns, and this computation time (delay) is examined as the clock rotation. With the computation time 0.042 ns clock cycle period. Floating point fused multiply add unit can be operated with 16000 MHz clock frequency. Floating point pipeline and kogge stone adder are implemented using Spartan 6. And the observation of result showing that the delay is decreased by 32% and low power consumption is saved by 48% [1].