Hurdles for a DRAM-based Match-Action Table
Curt Beckmann, Ramkumar Krishnamoorthy, Han Wang, Andre Lam, Changhoon Kim · 2020
The P4 language has gained traction as a tool for programming packet processing pipelines. Current commercial use is focused on single-chip pipelines, but as network scales grow, the need to enable programmability of multi-chip pipelines grows as well. Combining a P4-capable ASIC with a DRAM scale match-action table is a useful exercise for studying the obstacles to delivering efficient tools for programming multi-chip pipeline systems. We have constructed a demonstration environment for investigating those obstacles and learning what compilation tuning mechanisms will be required in the p4 tools used by system designers.