Design of Area and Power Efficient Hybrid Floating Point Number System (HNS) Arithmetic Unit for DSP Applications
Kaustubh Hitendra Bagul, P. P. Shingare · 2018
A power and area efficient 32-bit hybrid floating point number system (HNS) arithmetic unit is proposed and implemented for digital signal processing (DSP) applications. Inputs and outputs of this unit are in standard IEEE 754 32-bit single precision (SP) format. The proposed hybrid unit performs various floating point operations like addition, subtraction, multiplication, division, square and square root with 1 or 2 clock cycles. An internal core adopts a logarithmic domain (LNS) for complex arithmetic operations like multiplication, division, square, square root and floating point (FP) domain for addition and subtraction. For inter-conversion of LNS and FP, 8 region piecewise linear logarithmic and antilogarithmic converters are proposed with 0.05% and 0.31% maximum conversion error, respectively and with 8 to 10-bit accuracy. The proposed design is implemented in Verilog and simulated and synthesized with XILINX ISE and cadence encounter tool. This unit operates at 90 MHz on Artix 7 device and consumes 1.12 mW power at 1.1V supply for 45 nm CMOS technology and shows considerable reduction in power and area.