In Situ Caching using Combined TTL-FIFO Algorithm
Gasydech Lergchinnaboot, Peraphon Sophatsathit, Saranya Maneeroj · 2019
This research proposes an algorithmic cache arrangement scheme to efficiently utilize existing hardware that are currently plagued with memory wall problem. The proposed scheme exploits straightforwardness of First-in, First-out (FIFO) scheduling algorithm and in situ placement technique. FIFO allows the proposed scheme a fair caching of processes. In situ replacement economically utilizes spaces by replacing the expired process with a new process in the same memory space without flushing. This combination helps reduce operating overheads, which in turn lower power consumption. The benefits of their simplicity and hardware implementable will accelerate operational speed that eventually closes the gap between processing speed and memory access/retrieval speed, thereby lessens the memory wall problem.