Securing Hardware Accelerators Using Multi-Key Based Structural Obfuscation
Anirban Sengupta, Mahendra Rathor, Somesh Sanjay Patil, Naukudkar Gaurav Harishchandra · Letters of the IEEE Computer Society · 2020
A hardware accelerator is a pivotal component of a system-on-chip (SoC) employed in modern electronic systems. However, the design of hardware accelerators can be infected by inserting malicious logic (hardware Trojan) through reverse engineering (RE) by an adversary. Rising threats of RE and Trojan necessitates the security of hardware accelerator based SoCs. The proposed methodology secures the hardware accelerators using a novel structural obfuscation using key-driven transformation techniques such as key-based loop unrolling, key-based partitioning, key-based redundant operation elimination and key-based tree height transformation, which makes the design unobvious (non-interpretable) to an attacker. The results of the proposed approach on DSP hardware accelerators indicated 2.3× enhancement in strength of obfuscation (at gate level) compared to a recent approach (indicating enhanced security), at nominal design cost.