A Parameterized and Minimal Resource Soft Processor for Programmable Logic
Christopher L. Felton, Barry K. Gilbert, Clifton R. Haider · 2019
Incorporating a soft processor in a programmable logic system, e.g. a field programmable gate array (FPGA), often requires using a substantial percentage of the logic cells (LC), notably on low-power devices. In this work we present a 32-bit RISC-V soft processor design that uses a serial arithmetic logic unit (ALU). The design can be configured to use less than 5% of the LC resources in a 5K LC low-power FPGA device. Small occupancy soft processors enable complex control and ancillary support to the principal processing and transport paths.