Exploring Opencl on a CPU-FPGA heterogeneous architecture research platform (HARP)
Thomas Faict, Erik H. D'Hollander, Dirk Stroobandt, Bart Goossens · Ghent University Academic Bibliography (Ghent University) · 2019
FPGA and OpenCL: do they deliver a HPC hardware accelerator?Intel introduced the Heterogeneous Architecture Research Platform (HARPv2) [1].The platform interconnects a CPU (Broadwell Xeon) and a Field-Programmable Gate Array (Intel Arria 10 GX) through a high speed, low latency QPI/PCI data path providing cache coherency and shared memory.To program the FPGA, OpenCL, a High Level Synthesis (HLS) language, is made available [2].By using HLS, a faster design cycle can be achieved compared to programming in a traditional Hardware Description Language (HDL).This, however, comes at the cost of having less control over the hardware implementation.We will investigate how efficiently OpenCL can be applied on the HARP platform. I. HARP performance enhancing featuresThe integrated package of a Xeon CPU and a Arria 10 GX FPGA features a Cache Interface and System Protocol layer (CCI-SPL), supporting virtual memory address translation and cache coherency.The user generated Accelerator Functional Unit has access to DDR shared memory.The integrated package provides several performance enhancements.