Multi‐core hardware realisation of the quasi maximum likelihood PPS estimator
Nevena R. Brnović, Veselin N. Ivanović, Igor Djurović, Marko Simeunović · IET Computers & Digital Techniques · 2020
Multi‐core hardware realisation of the quasi maximum likelihood algorithm as the state‐of‐the‐art estimator of polynomial phase signals (PPSs) is proposed in this study. Developed multiple‐clock‐cycle realisation is suitable for real‐time implementation. To prove this, the proposed design is implemented on a field programmable gate array circuit. The hardware realisation is tested and verified on PPSs corrupted with various amounts of the Gaussian noise. Obtained results are compared with software simulations showing excellent match between the proposed system‐based and the software‐based outputs.