Design and Analysis of Logic Encryption Based 128-Bit AES Algorithm: A Case Study
Surbhi Chhabra, Kusum Lata · 2018
In today's world, globalization of semiconductor industry leads to piracy and overbuilding of integrated circuits (ICs) and making it accessible for untrustworthy elements to insert hardware trojans. The solution to this problem is logic obfuscation which is used to encrypt the design by inserting additional gates so that valid output is produced only when the valid key is applied to these additional gates. This paper discusses the design and analysis of logic obfuscation based 128-bit AES algorithm. In this paper logic obfuscation based 128-bit AES algorithm is designed and simulated using Xilinx Vivado 2016.2. Results show that with logic obfuscation 128 bit AES algorithm offer the higher level of security and implementation flexibility with the small area overhead of 0.88%. The robustness of the proposed algorithm is also analyzed in the form of throughput and efficiency. The authors also presented the power consumption and analyzed the power overhead of 0.015W of the proposed algorithm using basys-3 FPGA. For the security analysis, hamming distance and avalanche effect have been used as evaluation metrics. Specifically, the proposed technique maximizes the uncertainty for an attacker as this technique manage to achieve 50% hamming distance and 40% avalanche effect between the correct and incorrect outputs when an invalid key is applied.