Self-timed LUT Layout Simulation
Alexandra Yu. Skornyakova, Ruslan V. Vikhorev · 2020
The paper proposes Self-timed LUT for FPGAs. The following options are considered: Self-timed LUT with dual channel, spacer circuit and indicator; DC- Self-timed LUT; DNF - Self-timed LUT. Simulation LUT in the system of automated design of specialized (custom) integrated circuits Microwind.