A Learning Framework for Versatile STL Controller Synthesis
Peter Varnai Dimos, Dimos V. Dimarogonas · 2019
In this paper, we aim towards providing a practical framework for learning to satisfy signal temporal logic (STL) task specifications for systems with partially unknown dynamics. We consider STL tasks whose satisfaction can be guaranteed by enforcing a priori known temporal specifications imposed on the atomic propositions that compose them. First, a neural network is trained offline as a control policy to satisfy such temporal specifications while also minimizing a target cost, such as the input energy of the system. The obtained controller then serves as a guide that aids exploration while learning to satisfy any specific STL task optimally using policy improvement, greatly increasing the sample efficiency of the procedure. The promise of the approach towards a versatile STL learning framework is demonstrated through simulations.