Efficient Implementation of Low Mismatch IQ Signal Generator Based on 90° Differential Phase Shifting
G.D Satishkumar, S. Raghu, Punithavathi Duraiswamy · 2018
This paper presents a two-step optimization technique for designing a VLSI architecture for the generation IQ signal using dual FIR filters to reduce the area and power consumption. The first step reduces the number of constant multiplications from 2N to N while designing the phase-orthogonal FIR filters that provide 90° differential phase shift. In the second step, a hardware architecture is developed and the constant multipliers are shared between the two FIR filters taking advantage of the time reversal property of the two filters. This reduces the number of constant multipliers further from N to N/2. Transposed FIR filter structure is used and the N/2 constant multipliers are implemented using CSD multipliers. This dual filter approach and the optimization technique have resulted in very less amplitude and phase error compared to the widely used Hilbert transform FIR filter approach. The FPGA implementation of the architecture gives a phase and amplitude error of -0.1649° and 0.0002 for filter of order 26 and -0.2177° and 0.0053 for filter of order 32 respectively. This performance comes at the cost of 1.54 times (not twice) the area of the Hilbert transform method.