LFSR-based Bit-Serial $GF(2^m)$ Multipliers using Irreducible Trinomials
José Luis Imaña · IEEE Transactions on Computers · 2020
In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field GF(2m) generated by irreducible trinomials is presented. Bit-serial GF(2m) PB multiplication offers a performance/ area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR (Linear-Feedback Shift Register) and can perform a multiplication in m clock cycles with a constant propagation delay of TA þ TX. These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands fort different finite fields GF(2m) generated by t irreducible trinomials simultaneously in m clock cycles with the inclusion of t(m - 1Þ flipflops and tm XOR gates.