A Comparative Study of Single-Iteration Scheduling Algorithms for Input-Queued ATM Switches
Mervat Said, Zeiad El-Saghir, Nawal Ahmed El-Fishawy · Menoufia Journal of Electronic Engineering Research · 2019
Most high-speed switches use input queued architectures. These architectures generally utilize iterative scheduling algorithms for their operation. Iterative schedulers require high time complexity, so their efficiency is low, especially under heavy load conditions. To overcome this drawback, a new trend has emerged in the field of scheduling algorithms, by introducing so-called non-iterative scheduling algorithms. These algorithms achieve a maximum matching of I/O mapping in a single iteration, so they achieve high throughput and reduce the switch delay as they require less time complexity. This paper is a comparative study of the most efficient single-iteration algorithms used for scheduling cells in high-bandwidth input-queued ATM switches. Five algorithms were evaluated in terms of the throughput and the switch latency, including PIM-1, iSLIP-1, SSRR, SRRR, and CHRF algorithms.